TSMC Starts Development on 2nm Process Node, but What Technologies Will It Use?
TSMC has been firing on all thrusters for the past few years, and the firm seems confident that’s going to continue into the next few years. With 7nm in wide production and 5nm high volume manufacturing on-track, TSMC is looking even beyond the 3nm node and declaring that early 2nm research has now begun.
We don’t know what specific technologies TSMC will deploy at 2nm and the company has barely acknowledged the beginning of its research, so it’s safe to say even it isn’t sure yet, but we can look at some of the broad expectations. The International Roadmap for Devices and Systems publishes periodic updates on the future of silicon technology, including a 2018 chapter called “More Moore,” (this refers to the ongoing scaling of Moore’s Law). In it, they mapped out the expected technological developments for future nodes in broad strokes:
The IDRS expects GAA (Gate-all-around) FETs and FinFETs to share the market at 3nm, with GAAFETs replacing FinFETs at 2nm. The acronym “LGAAFETS” refers to lateral gate-all-around FETS, or GAAFETs in a traditional 2D processor. Vertical Gate-all-around FETs would be used in yet-to-be-developed 3D transistor structures.
Surprisingly, the IDRS projects we’ll still see 193nm lithography deployed as far out as 2034. I would have expected EUV to have conquered the market by this point for all leading-edge nodes, but I haven’t found an explanation on this point in the report yet.
The IDRS is predicting the deployment of so-called “high-NA” EUV. NA is a dimensionless number that characterizes the range of angles over which a system can accept or emit light. EUV, by its very nature, pretty much loves to do anything except be emitted, so developing optical systems that support effective EUV dosing over a larger range of angles has been a high priority. The alternative to high-NA EUV is to move immediately to multi-patterning EUV.
*collective groan from audience*
Everything people don’t like about multi-patterning in 193nm they really don’t like about multi-patterning with EUV. IDRS is forecasting that we’ll see high-NA systems first deployed at 2nm.
3D stacking technology isn’t projected to change much — die-to-wafer and wafer-to-wafer will be deployed on this node as well as 3nm. The next major node shift, in 2028, will introduce a suite of new technologies.
It isn’t clear what kind of performance scaling enthusiasts should expect. According to TSMC, the 5nm node is a huge leap for density (80 percent improvement) but only a small gain for power consumption (1.2x iso performance) and performance (1.15x iso power). Those are very small gains for a major node shift, and they imply we shouldn’t expect a lot of performance gains strictly from the node. Whether this will be the new norm or a temporary pause is still unclear.
Note that the IDRS estimate of 2025 for 2.1nm is based on forecasting they did in 2018. The IDRS does not claim to know the exact dates when Intel, TSMC, or Samsung will introduce a node. With 5nm launching in 2020, we might expect 3nm by 2022, and 2nm by 2024 – 2025, so the estimate looks reasonable.
One trend we expect to continue into the future is the way Intel and AMD are designing new capabilities to continue to improve performance now that clock speed isn’t on the table the way it used to be. Chiplets, HBM, EMIB, Foveros, and similar technologies all drive higher performance without relying on historic drivers like smaller transistors, lower supply voltage, and higher clocks. A great deal of effort is being spent to optimize material engineering and circuit placement as a means of improving performance or lowering power consumption, precisely because new nodes don’t deliver these improvements any longer without a great deal of additional work.