Intel’s 10nm Sapphire Rapids CPU Delidded, Photographed

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Intel’s is currently ramping volume on its Ice Lake-SP CPU, but die shots of its follow-up generation, Sapphire Rapids, have already leaked. To quickly recap: Up until now, Intel’s desktop and server processors have both been based on 14nm CPUs. Ice Lake-SP is Intel’s first 10nm server product and it uses the Sunny Cove CPU core.

Sapphire Rapids is the follow-up to Ice Lake-SP, and it’s not expected until 2022-2023. Following Intel’s nomenclature, it would be manufactured on the 10nm++ process, and it’s expected to use the same Willow Cove CPU architecture that powers Intel’s Tiger Lake mobile chips. The photos below were released by YuuKi_AnS:

A source has confirmed to THG that the chip is a Sapphire Rapids A2 sample, with 28 enabled CPU cores. We’re looking at LGA4677, if the rumors are true. Ice Lake-SP uses LGA4189, but it’s not surprising for Intel to swap to a new socket at the same time they add DDR5, PCIe 5.0, and chiplets. Previous leaks have also suggested at least some Sapphire Rapids products will support HBM memory. This would likely be confined to specific SKUs, however, since the HBM has to be integrated on-package.

Given that the LGA4677 socket is estimated at about 72mm x 54mm, there’s no way for the chiplets above to be anything less than huge. Much larger, in fact, than just a seven-core CPU array can account for. THG’s sources claim that Intel has packaged up to 14 cores per chiplet, for a total of 56 cores available. This is obviously an early, engineering sample processor, so only having 28 of the cores active wouldn’t be considered unusual.

One interesting difference between the AMD CPUs and this ES CPU is the gap — or lack thereof — between the die. On an AMD Threadripper or Epyc, there’s four distinct chiplets located around the I/O die:

Image by Fritzchens Fritz, CC0 1.0

The Intel CPU has no I/O die, though there’s an Altera Max 10 FPGA off-package. Keeping the CPUs physically closer together will cut latency and reduce the power consumption spent on chiplet-to-chiplet communication.

These are engineering samples for a CPU we don’t expect to see for 18-24 months, so we’d take them with a shaker of salt more so than a grain, but what we see here is broadly what we’d expect to see. Intel has previously stated it believes its advanced packaging technology is a meaningful differentiator between itself and AMD. We’ll see if AMD pulls its Epyc chiplets back together into a clustered configuration over the next few product generations, but for now it looks like Intel and AMD may pursue different strategies when it comes to handling intra-chip communication.

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