Future 256-Core AMD Epyc CPU Might Sport Remarkably Low 600W TDP
There’s a rumor making the rounds that AMD’s future Zen 5 CPU family, codenamed Turin, might have a TDP as high as 600W. These future CPUs will supposedly be available in at least two two configurations of 192 cores / 384 threads and 256 cores / 512 threads.
EPYC Turin has a max cTDP of 600W 🔥
— ExecutableFix (@ExecuFix) October 28, 2021
Take this rumor with a mountain of salt. AMD has not said much publicly about Zen 5. With Genoa expected to jump to 96 cores with Zen 4, a leap to 256 cores with Zen 5 would be a large jump indeed — especially since there might not be a die shrink between Zen 4 (5nm) and Zen 5. Alternately, it’s possible that AMD might release a Zen 4 and Zen 4+ before a theoretical Turin CPU launched later.
No matter what, this is a chip we wouldn’t expect to see for another 24 – 36 months. AMD is almost certainly still working on the Zen 5 architecture and considering the configurations it might build relative to where Intel and its potential ARM competition will be in the future.
A number of posts online are referring to a 600W TDP as a “monster,” but that depends on how you evaluate the situation. It’s true that we’ve never seen a desktop or x86 socket that could dissipate this kind of heat, but while 600W is quite high in absolute terms, it’s downright svelte when you consider how many cores this rumor suggests the future chip will offer.
Right now, an AMD Epyc 7763 has a TDP of 280W and 64 CPU cores. This works out to 4.375W per core if you assume the chip’s L3 caches and Infinity Fabric draw no power at all. A future 600W CPU with 256 cores is a chip that allocates no more than 2.34W per core; 1.86x less power than current Epyc CPUs. This implies quite a bit of near-term improvement in AMD’s performance per watt at a time when lithography-based improvements are shrinking every node. Feel free to enjoy some salt mountain at this point.
A CPU with this many cores isn’t going to be aimed at consumer markets. There are so-called “embarrassingly parallel” workloads in computing that can scale to very high core counts, but many of them have been optimized for GPU execution over the last decade. Perhaps more pertinently, a system with 256 cores and the same eight cores per memory channel ratio as current Epyc CPUs would need a 32-channel memory interface to keep the cores fed. While there are ways to reduce the need for memory bandwidth, large L3 caches and on-package HBM aren’t cheap.
A rumor like this is difficult to completely dismiss because the claims it makes are in line with some long-term projections for where CPU development is headed. AMD has aggressively increased x86 core counts with Ryzen. It has publicly stated that it adopted chiplets partly for their superior scaling characteristics relative to conventional monolithic designs.
A 256-core CPU isn’t all that large when you consider that the Ampere Altra Max already offers a 128-core single-socket solution. While it’s an aggressive roadmap for AMD given that the company is “only” expected to ship 96-core chips in 2022, one could argue it shows AMD taking the threat of a resurgent Intel seriously, and that the company intends to retain the leadership position it opened against its rival while Intel was stuck on 14nm.
I don’t have any inside information on when/if AMD intends to ship a 256-core CPU, but it’s definitely something the company has thought about. Silicon development timelines are long and engineers are accustomed to planning for what’s likely to be available 24-36 months in the future. The many-core research projects from a decade ago showed that a balance must be struck between the number of cores and the amount of work those cores are capable of doing. Whether AMD steps up to 256 cores or not will depend in part on how moving from 128 to 256 cores would impact the CPU’s ability to perform useful work in more lightly threaded applications.
As for the 600W figure, that’s not particularly large for a theoretical 256-core CPU. Such a system could wind up saving power by eliminating redundant hardware in multiple chassis that would otherwise be required to provide the same number of cores.