AMD’s Mark Papermaster Dishes the Goods on Zen 3
As we head towards November 5 and the upcoming launch of AMD’s 5000 Series and the Zen 3 architecture, a lot of folks have had questions about various facets of the Zen 3 design. AMD shared details on the chip earlier this month and CTO Mark Papermaster was evidently willing to sit down with members of the technical press as well. In a recent interview with Anandtech, Papermaster shed light on the future of AMD designs, its IPC gains, process nodes, fabric technology, security, silicon binning, and much more. I’m going to cover the major points, but there’s plenty of additional data in the extensive interview.
Performance, Process, and Power Consumption
According to Papermaster, rearchitecting the Zen 3 core with an 8-core complex design and full access to its 32MB L3 cache was “the single biggest lever” in reducing overall latency in gaming applications. While AMD once implied that it would move to a second-generation 7nm node for this product, this guidance has since changed. The improvements it speaks of are the gains we would expect from any maturing process.
So if you look at the transistors, they have the same design guidelines from the fab. What happens of course in any semiconductor fabrication node is that they are able to make adjustments in the manufacturing process so that of course is what they’ve done, for yield improvements and such. For every quarter, the process variation is reduced over time. When you hear ‘minor variations’ of 7nm, that is what is being referred to.
As for the power efficiency improvements that give Ryzen its 24 percent improved performance per watt, Papermaster ascribes the boost to better granularity and responsiveness, as well as efficiency gains from the new eight-core complex. Further improvements to Precision Boost and to the low-level sensor network blanketing the chip have also helped AMD to reduce power consumption without changing nodes for 7nm or 12nm. The I/O die contains some unspecified “incremental improvements,” but Papermaster advises fans to look for larger gains in AMD’s next round of generational improvements.
Papermaster’s comments on specific load/store improvements are worth quoting directly:
The load/store enhancements were extensive, and it is highly impactful in its role it plays in delivering the 19% IPC. It’s really about the throughput that we can bring into our execution units. So when we widen our execution units and we widen the issue rate into our execution units it is one of the key levers that we can bring to bear. So what you’ll see as we roll out details that we have increased our throughput on both loads per cycle and stores per cycle, and again we’ll be having more details coming shortly.
Note: AMD considers Zen 3 to be a full redesign of the original Zen architecture. This is a point we’ve actually heard from more than just him. The entire reason AMD has gotten this type of improvement out of the chip is that AMD rebuilt the core. The expected IPC + clock speed improvement for the 5000 series over the 3000 series is ~1.24x, though this may or may not apply to the 5950X the way it does the other CPUs. The 5950X is the most likely CPU to run into the TDP limits AMD builds into AM4.
Papermaster’s response to a question about new markets AMD might branch into is particularly interesting. According to him, AMD is not pursuing “the markets that may have a lot of media attention but are not well matched to the kind of high performance and incredible focus that we have at AMD. We want to deliver high performance at a value to the industry.” It is not clear what this means for the rumors of a Xilinx acquisition or if those rumors were credible in the first place. A Xilinx purchase would likely focus on AI and 5G, but AMD’s consistent messaging on chips is that it isn’t focused on adding narrow support for specific fields right now. As such, it isn’t clear if the CPU manufacturer would consider an FPGA business to be a complementary purchase.
As far as Zen 3 goes, we’ll see what they’ve brought to the table, come November 5.